The invention relates to a semiconductor chip and a lead frame on which the semiconductor chip is to be mounted.
With the advent of smaller (less than 0.5 xcexcm) semiconductor technologies, complex functionality and systems can be integrated on a single chip. However, cost effective packaging of such devices is a challenge, due to the large number of external functional and power supply pins which are required for such devices. The interface between the external package and the chip core is normally through bond pads on the silicon surface of the chip. These can take up a large proportion (sometimes greater than 50%) of the total surface area of the silicon chip.
Accordingly, the size of a silicon chip is limited to a large extent by the number of pads that are required and the space that the pads occupy on the surface area of the silicon chip.
With current silicon chip designs the pads are arranged in side by side relationship on the surface of the silicon chip adjacent the edges of the chip to permit easy access for wire bonding from the pads to the corresponding pins on the lead frame. Hence, if a large number of pads are required for a specific chip design, it is necessary to increase the edge length of the silicon chip to accommodate the additional pads. This inevitably causes an increase in the size of the silicon chip.
There is also a further problem with trying to reduce the size of a packaged silicon chip. Pins are required on the lead frame which are coupled to the bond pads on the silicon chip. It is the pins which couple the bond pads to external devices and supply power to the silicon chip. Therefore, if a silicon chip has a large number of pads then a correspondingly large number of pins are also required. The large number of pins has the problem of increasing the final package size of the silicon chip.
One attempt at reducing the total number of pins has involved reducing the number of power supply pins which are required by xe2x80x9cdouble bondingxe2x80x9d two power supply bond pads to one pin.
However, this has the disadvantage that it does not permit strategic placement of the power supply bond pads on the surface of the silicon chip. This is important to achieve good noise performance on the chip.
In accordance with a first aspect of the present invention, a semiconductor chip comprises a semiconductor substrate having an electronic circuit thereon and a number of bond pads thereon, the bond pads being coupled to the electronic circuit and permitting power to be supplied to the electronic circuit and signals to be input to and output from the electronic circuit, the bond pads being arranged on the surface of the substrate such that at least some of the pads are separated from the edge of the substrate by other bond pads.
An advantage of the invention is that by not having all the bond pads adjacent to an edge of the substrate, it is possible to minimise the required surface area of the semiconductor substrate.
Preferably, the at least some pads are arranged such that they are offset from the immediately adjacent bond pads which are adjacent to the edge of the semiconductor substrate.
In accordance with a second aspect of the present invention, a lead frame comprises a die pad adapted to have a semiconductor chip mounted thereon and a number of contact pins adapted to be electrically coupled to bond pads on a semiconductor chip mounted on the die pad, in use, two of the contact pins being electrically coupled to each other by a contact strip which extends along at least a portion of an edge of the die pad, and the contact strip being located between the die pad and some of the other contact pins.
An advantage of this aspect of the invention is that by providing two contact pins which are electrically interconnected by a contact strip, it is possible to have a lead frame with a power supply contact pin which extends from one side of the die pad to the opposite side of the die pad such that bond pads on the semiconductor chip may be electrically connected to any point on the contact strip extending between the two contact pins. This has the advantage that it is possible to arrange the power supply bond pads on the semiconductor chip to achieve, for example, good noise performance, while still permitting the power supply bond pads to be electrically coupled to the power supply contact pins. It also has the advantage that only two contact pins are required for a number of power supply bond pads.
Typically, two pairs of contact pins may each be electrically coupled to each other, each pair being electrically coupled by a respective contact strip, such that the first contact strip is located between an edge of the die pad and the second contact strip, and the second contact strip is located between the first contact strip and some of the other contact pins. This has the advantage of permitting two different supply voltages to be supplied to the same silicon chip.
If necessary, more pairs of pins could be electrically coupled to each other using further contact strips in order to provide further power supplies, if necessary.
Preferably, the contact strip extends along the full length of at least one edge of the die pad, which is preferably the edge of the die pad which would be adjacent to the edge of the semiconductor chip which has the power supply pads adjacent to it, when the semiconductor chip is mounted on the die pad.
Preferably, the die pad is adapted to have a silicon chip in accordance with the first aspect mounted thereon.